1. Field of the Invention
The present invention relates to a semiconductor device having a high-reliability high-performance capacitor, and to a method of manufacturing the semiconductor device.
2. Description of the Related Art
In the integrated circuits (ICs) that handle analog signals, capacitors, resistors, inductors, and other passive devices become important constituent elements of the ICs. In the past, these passive devices have been difficult to build into IC chips and have therefore been mounted as external components on substrates. In recent years, however, incorporating the passive devices into IC chips has been attempted actively in order to meet the strong needs of faster system operation and space saving.
One of the most common techniques for forming a capacitor in an IC chip is by using a capacitor structure having an insulator interposed between the upper and lower layers of polysilicon. This type of capacitor, because of its structure, is called the PIP capacitor (PIP: Polysilicon-Insulator-Polysilicon). This capacitor, however, has problems including the ones that the use of an electrode material which contains polysilicon increases resistance, and that since the deposition temperature of the polysilicon exceeds the maximum permissible temperature in a wiring process, the capacitor must be formed near a silicon substrate and this also increases coupling capacitance. An MIM (Metal-Insulator-Metal) capacitor with an insulator interposed between an upper and a lower metal electrode is drawing attention as a method of solving those problems.
Some of the features, characteristics, and problems that the MIM capacitor has are described below using the process diagrams of a conventional working example that are shown in FIGS. 2A, 2B, 3A, and 3B.
First, as shown in FIG. 2A, a titanium nitride film with a film thickness of 50 nm, an aluminum alloy film with a film thickness of 400 nm, and another titanium nitride film with a film thickness of 50 nm are formed in that order on a substrate 100 having semiconductor devices formed thereon. After that, a first etching mask 600 is formed in a desired area by lithography, and then first metal wiring 700 including a first barrier metal layer 205 made of a 50-nm-thick titanium nitride film, a first aluminum layer 206 made of a 400-nm-thick aluminum alloy film, and a second barrier metal layer 207 made of a 50-nm-thick titanium nitride film, is formed by conducting a dry etching process using the first etching mask 600.
Next, as shown in FIG. 2B, a first interlayer dielectric layer 304 made of a 1000-nm-thick silicon dioxide film is formed with a plasma chemical vapor deposition (CVD) method in such a manner as to cover the first metal wiring 700. After this, planarity of the first interlayer dielectric layer 304 is increased using a chemical-mechanical polishing method and then an opening 501 formed in the first interlayer dielectric layer in order for the first metal wiring 700 to become exposed is provided using lithography and dry etching. The area where the opening is provided serves as an MIM capacitor. Next, a dielectric layer 400 made of a 50-nm-thick silicon dioxide film is formed by conducting a plasma CVD process using tetraethoxysilane as a raw material, in such a manner as to cover the first metal wiring 700 exposed inside the opening 501 formed in the first interlayer dielectric layer. Next, in order to form interconnect via plugs for establishing electrical connections to the portions of the first metal wiring that exist in areas other than the MIM capacitor, a second etching mask 601 having an opening in a desired area is formed on the dielectric film 400 and a second opening 502 is formed by conducting a dry etching process using the second etching mask 601.
Furthermore, as shown in FIG. 3A, a tungsten film is formed by sputtering and CVD in such a manner as to fill in the openings formed in the first interlayer dielectric layer 304, then the tungsten film portions in areas other than the openings are removed by chemical-mechanical polishing, and a first conductive plug 250 and a second conductive plug 251 are formed. Next, as shown in 3B, a titanium nitride film with a film thickness of 50 nm, an aluminum alloy film with a film thickness of 400 nm, and another titanium nitride film with a film thickness of 50 nm are formed in that order. After this, second metal wiring 701 including a third barrier metal layer 208 made of a 50-nm-thick titanium nitride film, a second aluminum layer 209 made of a 400-nm-thick aluminum alloy film, and a fourth barrier metal layer 210 made of a 50-nm-thick titanium nitride film, is formed in a desired area by lithography and dry etching. The use of the above processes makes it possible to form an MIM capacitor constructed of the first metal wiring 700, the dielectric film 400, the first conductive plug 250, and the second metal wiring 701. Hereinafter, the MIM capacitor that is formed, pursuant to the above processes, is referred to as conventional example 1 or as the MIM capacitor based thereon.
The MIM capacitor based on conventional example 1 can be formed during a wiring process since the forming temperature of electrodes is 450° C. or less. Also, since a metallic material of low electrical resistance can be used for the electrodes, the use of the MIM capacitor makes it possible to solve the problems that the PIP capacitor poses.
The thus-formed MIM capacitor, however, has the disadvantage that it cannot easily enhance performance. In the foregoing technique, after interconnect via plugs have been formed in the wiring positioned in the underlayer serving as a lower electrode, a dielectric film is formed using the CVD method. In general, silicon dioxide films and silicon nitride films can be formed by CVD at temperatures below 450° C., the maximum permissible temperature in wiring, and the two types of films are about 4 εr and 7 εr, respectively, in relative permittivity. Since the minimum film thickness of the nondefective films which can be formed in the interconnect via plugs each having a depth equal to or greater than wiring height is about 50 nm, the maximum permissible capacitance density in the case of silicon dioxides is 0.7 fF per square micrometer, and that of silicon nitrides is 1.2 fF per square micrometer. Accordingly, there have been the problems in that it is difficult to reduce the area occupied by MIM elements in one IC chip and thus in that the IC chip itself increases in area.
Using materials (high-permittivity materials) whose relative permittivities are higher than those of silicon dioxides or silicon nitrides is being studied as a method of solving the above problems. Typically, tantalum oxides, hafnium oxides, titanium oxides, and the like are being studied as materials whose relative permittivities are 20 εr or more. A conventional example of the MIM capacitor forming processes using such a high-permittivity material is described below using FIGS. 4A to 4C.
As shown in FIG. 4A, a first barrier metal film 200 made of 50-nm-thick titanium nitride, a first aluminum film 201 made of a 400-nm-thick aluminum alloy, and a second barrier metal film 202 made of 50-nm-thick titanium nitride, and a dielectric film 400 and an upper electrode 203, made of 50-nm-thick tantalum oxide and 50-nm-thick titanium nitride, respectively, by use of reactive sputtering, are formed in that order on a substrate 100 having semiconductor devices formed thereon. After that, a first etching mask 600 is formed in a desired area by lithography.
Next, as shown in FIG. 4B, after the upper electrode 203 and the dielectric film 400 are patterned using the first etching mask 600, a second etching mask 601 is formed using lithography and then first metal wiring 700 including a first barrier metal layer 205, a first aluminum layer 206, and a second barrier metal layer 207, is formed by dry etching.
Furthermore, as shown in FIG. 4C, after a first interlayer dielectric layer 304 made of a 1000-nm-thick silicon dioxide film is formed using plasma chemical vapor deposition (CVD), the first interlayer dielectric layer 304 is made planar by chemical-mechanical polishing. After this, a patterned upper electrode 204 or the first metal wiring 700 is exposed by forming an opening using lithography and dry etching, and then a first conductive plug 250 made of tungsten and connected to the patterned upper electrode 204, and a second conductive plug 251 made of tungsten and connected to the first metal wiring 700 are formed in the opening. Finally, second metal wiring 701 including a third barrier metal layer 208 made of a 50-nm-thick titanium nitride film, a second aluminum layer 209 made of a 400-nm-thick aluminum alloy, and a fourth barrier metal layer 210 made of a 50-nm-thick titanium nitride film, is formed in a desired area by lithography and dry etching. The use of the above processes makes it possible to form an MIM capacitor made up of the first metal wiring 700, a patterned dielectric film 401, the patterned upper electrode 204, the first conductive plug 250, and the second metal wiring 701. Hereinafter, the MIM capacitor that is formed, pursuant to the above processes, is referred to as conventional example 2 or as the MIM capacitor based thereon.
The MIM capacitor based on conventional example 2 can use a 50-nm-thick tantalum oxide (relative permittivity: 24 εr), whereby it becomes possible to achieve a capacitance density of 4 fF per square micrometer and hence to reduce the area of the capacitor in an IC chip. The thus-formed MIM capacitor, however, has the disadvantages that it is low in dielectric breakdown voltage and significant in leakage current. A structure in which the upper electrode 204 and dielectric film 401 patterned at the end of the MIM capacitor match at the respective ends and the first metal wiring 700 serving as a lower electrode is positioned directly under the ends, is employed in the above technique. Since the end of the dielectric film has a large number of defects, increases in leakage current and decreases in dielectric breakdown voltage are liable to occur in the structure where the end of the dielectric film directly abuts the upper electrode and the lower electrode. However, in the process diagram of FIG. 4A, after the upper electrode 203 and the dielectric film 400 have been patterned using the first etching mask 600, the ends of the dielectric film 401 and upper electrode 204 which have been patterned by conducting lithographic and dry etching processes once again can be formed in shifted form. Thus, the upper electrode 204 and dielectric film 401 patterned at the end of the MIM capacitor can be prevented from matching at the respective ends. At the same time, however, the above technique has the disadvantage that since the upper electrode 203 is dry-etched on the dielectric film 400, dielectric breakdown strength is reduced by the plasma damage and/or local film thinning-down occurring in the area located directly under the end of the patterned upper electrode 204 on the dielectric film 400.
Employing a structure having a dielectric film and a second dielectric layer interposed directly under the end of the upper electrode of the MIM capacitor is being proposed as a method of solving the above problems. This makes it possible to minimize the leakage current increases and dielectric breakdown voltage decreases occurring at the end of the MIM capacitor. A conventional example of such MIM capacitor forming processes is described below using FIGS. 5A to 5C and 6A to 6C.
As shown in FIG. 5A, first metal wiring 700 including a first barrier metal layer 205 made of a 50-nm-thick titanium nitride film, a first aluminum layer 206 made of a 400-nm-thick aluminum alloy, and a second barrier metal layer 207 made of a 50-nm-thick titanium nitride film, is first formed on a substrate 100 having semiconductor devices formed thereon. After this, a first intermediate layer 300 made of 100-nm-thick silicon dioxide is formed on the entire surface of the first metal wiring 700 by plasma CVD.
Next, as shown in FIG. 5B, after the surface of the first metal wiring 700 is exposed by forming an opening in the first intermediate layer 300 by lithography and dry etching. After this, a dielectric film 400 made of a 50-nm-thick tantalum oxide, and an upper electrode 203 made of a 50-nm-thick titanium oxide film are sequentially formed, both by reactive sputtering, in such a manner as to cover the opening, and then a first etching mask 600 is formed in a desired area by using lithography.
Furthermore, as shown in FIG. 5C, a patterned dielectric film 401 and a patterned upper electrode 204 are formed by conducting a dry etching process using the first etching mask 600. At this time, an etching residue 800 made up of the upper electrode 203 and the dielectric film 400 is present on the sidewalls of the first metal wiring 700.
Next, as shown in FIG. 6A, after a first interlayer dielectric layer 304 made of a 1000-nm-thick silicon dioxide film is formed using plasma chemical vapor deposition (CVD), the first interlayer dielectric layer 304 is made planar by chemical-mechanical polishing. After this, a patterned upper electrode 204 or the first metal wiring 700 is exposed by forming an opening using lithography and dry etching, and then a first conductive plug 250 made of tungsten and connected to the patterned upper electrode 204, and a second conductive plug 251 made of tungsten and connected to the first metal wiring 700 are formed in the opening. Finally, as shown in FIG. 6B, second metal wiring 701 including a third barrier metal layer 208 made of a 50-nm-thick titanium nitride film, a second aluminum layer 209 made of a 400-nm-thick aluminum alloy, and a fourth barrier metal layer 210 made of a 50-nm-thick titanium nitride film, is formed in a desired area by combining sputtering, lithography, and dry etching. The use of the above processes makes it possible to form an MIM capacitor made up of the first metal wiring 700, a patterned dielectric film 401, the patterned upper electrode 204, the first conductive plug 250, and the second metal wiring 701. Hereinafter, the MIM capacitor that is formed, pursuant to the above processes, is referred to as conventional example 3 or as the MIM capacitor based thereon.
For the MIM capacitor based on conventional example 3, the upper electrode 204 and dielectric film 401 patterned at the end of the MIM capacitor match at the respective ends. However, since the first intermediate layer 300 is formed as another dielectric film directly under the ends, it becomes possible to minimize the leakage current increases and dielectric breakdown strength decreases occurring at the end of the MIM capacitor. The thus-formed MIM capacitor, however, has several disadvantages, which can be broadly divided into two. One is that as shown in FIG. 6B, since the high-permittivity tantalum oxide and the conductive titanium nitride are liable to remain as the etching residue 800 on both sides of the adjacent first metal wiring 700, coupling capacitance of the adjacent first metal wiring 700 and/or a wiring-to-wiring leakage current could increase. The other disadvantage becomes a problem particularly in areas of a narrow wiring pitch. This problem refers to one due to the fact that if the first metal wiring 700 is of a narrow wiring pitch, most of the volume between adjacent wiring portions is occupied by the first intermediate layer 300. The ICs in recent years are required to minimize interconnect coupling capacitance in order to meet the needs of further improved operating speed. Accordingly, a dielectric film formed from a material of a relative permittivity of as small as about 3.5 εr or less, called a low-k material, is usually used as a dielectric film around wiring. According to conventional example 3, however, as shown in FIG. 6C, since the volume between adjacent wiring portions is occupied by the first intermediate layer having a relative permittivity of as high as about 4 εr, there is little room for a low-k material to enter, which, in turn, significantly obstructs reduction in the coupling capacitance of the wiring (refer to, for example, Japanese Patent Laid-open Nos. 2001-320026, 2003-188264, and 2003-282719).
The problem that the present invention is to solve is that in an MIM capacitor that uses, as a dielectric film, a high-permittivity dielectric film (such as a tantalum oxide film) that can enhance the MIM capacitor in capacitance density, suppressing an increase in leakage current and a decrease in dielectric breakdown strength causes an increase in leakage current between adjacent wiring portions, and/or an increase in interconnect coupling capacitance, in the lower metal wiring of the MIM capacitor that forms part of its lower electrode.